1. Field
The following description relates to a wafer level package and a method of manufacturing the same.
2. Description of Related Art
With the recent trend for the miniaturization of semiconductor elements, interest in wafer-level packaging technology has increased. Wafer-level packaging technology refers to a semiconductor package technology involving packaging a wafer in which chips are not separated, unlike an existing scheme of separating chips from a wafer and packaging the individual chips cut from the wafer. In a wafer-level packaging method, the dicing of individual chips may occur after the packaging of the wafer.
Manufacturing a semiconductor device generally involves four separate processes, including a circuit design process, a wafer processing process, an assembly process and a testing process. Among these processes, the assembly process involves a wiring connection process and a package process. These processes involve a scheme of cutting individual chips from a wafer on which processing has been finished, attaching each of the individual chips to a small circuit board, connecting wirings, and then covering the small circuit board with a plastic package.
However, in a wafer-level packaging scheme, the package process is performed by a simple procedure of coating a photosensitive insulating material on a wafer, instead of applying a plastic as a package material on individual chips, connecting wirings, and reapplying an insulating material.
When the package technology as described above is applied, semiconductor assembly processes such as a wiring connection process and a plastic package process are shortened. In addition, a plastic packaging material, a circuit board, a wire for a wiring connection, and the like, that have been used to assemble a semiconductor in the related art are not required, such that manufacturing costs may be significantly reduced.